Continued physical scaling of mainstream silicon CMOS (complementary metal oxide semiconductor) technology has boosted the performance of the silicon devices in the last 40 years. A future direction could be the introduction of new channel materials with higher carrier mobility such as III-V compound semiconductors such as InSb, InAs, and InGaAs, which are very promising materials for high-speed and lower power computation applications. III-V materials in general have 50-100 times higher electron mobility than Si, and III-V quantum well field effect transistors present attractive merits over scaled Si transistors. Quantum well field effect transistors utilizing III-V materials have shown promise as an ultra-fast, very low power digital logic technology with their high electron mobility and saturation velocity.
Conventional quantum well devices are characterized by employing a narrow band gap quantum well layer sandwiched between two wide band gap barrier layers. The wide band gap barrier layers serve to confine carriers in the narrow band gap quantum well layer, and to reduce junction leakage and transistor off-state leakage current. In a quantum well, electrons and holes are free to move in 2-dimensions, and thus show distinctly different characteristics than in 3-dimensional silicon transistors. FIG. 1 illustrates a prior art quantum well transistor, comprising quantum well channel 15 located between source 13S and drain 13D, and controlled by gate 10. The quantum well channel is typically a low bandgap material, sandwiched between barrier layers 14 and 16 of higher bandgap material. The quantum well structure is fabricated on substrate 19. An optional buffer layer 18 can be formed between the substrate 19 and the quantum well structure for lattice matching.
However, today quantum well transistors are prone to high gate leakage and parasitic series resistance, especially for sub-micron devices with low operating voltage. There are few design improvements for III-V devices to reduce off-state leakage, perhaps due to the small number of transistors in integrated circuit, where high leakage current does not significantly affect the power requirement.
In contrast, silicon devices is fabricated in VLSI (very large scale integration) and even ULSI (ultra large scale integration), and thus designs with minimum off-state leakage current are required to provide reasonable power consumption. In addition, continual scaling of transistor devices also increases short channel effects, including an increased off-state drain to source leakage current, for example, in drain-induced-barrier-lowering and punch-through. Further, low operating voltage generally leads to low threshold voltage, which can lead to high off state leakage, which is the leakage current that occurs when the transistor is turned off.
One reliable and most likely used technique for preventing short channel effects in silicon field effect transistors is halo implants, which are generally known for their ability to stop unwanted source/drain leakage conduction, or punchthrough current. The halo architecture creates a localized dopant distribution near the source/drain regions and extends under the channel. FIG. 2 illustrates a prior art silicon channel transistor with halo implants, comprising source 23S, drain 23D, gate electrode 20 and gate dielectric 22 fabricated on substrate 29, together with source/drain extension 28S/28D and gate spacer 21. Angled implantation 27 forms pockets of halo implants 25, served to shape the distribution of the source and drain dopants, and thus controlling the leakage current in off-state.